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Chapter 1
Features:
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Five 16-bit timers
Two 8-bit prescalers & Two 4-bit divider
Programmable duty control of output waveform (PWM)
Auto reload mode or one-shot pulse mode
Dead-zone generator
All of the Timer outputs are connected to the system connector.
Clock output
At the global pins of the system connector there is a clock signal available
(BCLKOUT0), which is buffered by a clock buffer and can be chosen to be either MPLL
CLK, EPLL CLK, FCLK, HCLK, PCLK or DCLK. The source of this clock signal is the
CLKOUT0 port at the CPU, which can be programmed to different clocks, by the
CLKSEL0 register.
The following table shows the bits [6:4] of the CLKSEL0 register:
CLKSELO [6.4]
CLKOUT0
000
MPLL CLK
001
EPLL CLK
010
FCLK
011
HCLK
100
PCLK
101
DCLK0
11x
Reserved
CF/ATA
PC card
controller
The single-slot CF controller consists of 2 parts - PC card controller & ATA controller.
They are multiplexing from or to PAD signals. Users can select either PC card or
True-IDE mode operation. Default mode is PC card mode. The CF controller has a
top level SFR with card power enable bit, output port enable bit & mode select
(True-IDE or PC card) bit.
The PC card controller has 2 half-word (16 bit) write buffers & 4 half-word (16bits)
read buffers.
The PC card controller has 5 word-sized (32 bit) Special Function Registers.
Features:
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3 timing configuration registers
Attribute memory
Common memory
I/O interface
1 status & control configuration register
1 interrupt source & mask register
Timing configuration register consists of 3 parts - Setup, Command & Hold
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IDLE, SETUP, COMMAND & HOLD
45
ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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